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1. Field of the Invention
The present invention relates to determining offset between images such as images of an integrated circuit device, useful in automating operation of charged-particle beam systems.
2. The Prior Art
Charged-particle beam systems are commonly used in verification, characterization, design debug and modification of devices such as integrated circuits. For example, electron-beam (E-beam) systems are used to acquire and observe waveforms on internal nodes of a device as the device is exercised by application of a signal pattern to the external pins of the device, and to produce voltage-contrast images of the device. For waveform acquisition, a focused E-beam is directed at a node of the device, a signal dependent upon energy of detected secondary electrons is produced, and the signal is used to generate a waveform display. To produce a voltage-contrast image, the focused electron beam is scanned over the device, and a signal resulting from detection of secondary electrons is used to generate an image display.
Focused-ion-beam (FIB) systems are commonly used to perform three major functions: (1) etching/milling of structure, such as for cutting metal lines and drilling holes, (2) depositing material, such as for forming metal connectors and pads, and (3) scanning ion microscope (SIM) observation. These functions may be employed to modify the IC for failure analysis. For example, cutting and connecting metal lines aids in confirmation of an suspected failure mechanism or failure location, and milling holes in an insulation layer allows a "buried" conductor to be exposed or connected to a pad for improved E-beam or mechanical probing.
FIG. 1 is a block diagram showing the general structure of a prior-art charged-particle beam system. Commercially-available systems having such a structure include the "IDS 5000.TM." electron-beam test probe system and "IDS 7000 FIBstation.TM." focused-ion beam system, available commercially from Schlumberger Technologies, Inc., of San Jose, Calif. Such systems are described, for example, in U.S. Pat. Nos. 4,706,019 and 4,721,909 to N. Richardson and U.S. Pat. No. 5,140,164 to Talbot et al., the contents of which are incorporated herein by this reference.
As shown in FIG. 1, a charged-particle beam system 110 has three main functional elements: an electron-beam or FIB probe 112, a circuit exerciser 114, and a data processing system 116 which includes a display terminal 118. Data processing system 116 comprises a general purpose computer such as a Sun Microsystems workstation having a processor P with associated memory M and a data store D such as a disk drive. The circuit exerciser 114 may be a conventional integrated circuit tester, such as a model "S15.TM." tester (available from Schlumberger Technologies of San Jose, Calif. which can repeatedly apply a pattern of test vectors to the specimen circuit over a bus 124. The device (such as an IC) 126 is placed in a vacuum chamber 128 of probe 112. Data signifying the locations on device 126 at which the beam is to be directed are sent to probe 112 by data processing system 116 over a bus 122. Data processing system 116 may also be used to control circuit exerciser 114. System 110 can be controlled by an operator who inputs commands through display terminal 118.
As shown in FIG. 2, one such prior-art test probe 112 includes three elements mounted to a surface 225: a stage 226, a probe card 228, and a focused-beam column 229. Column 229 generates a charged-particle beam directed along axis 236. The electron beam passes through openings in surface 225 and probe card 228. The point at which the beam strikes device 126 (shown as a wafer in FIG. 2) is determined by the position of column 229 (controllable by means of an x-y stage 240) and by the deflection of the beam (controllable by means of x-y deflection coils 241 ).
Such systems combine on a single powerful workstation the display of a schematic circuit diagram, layout mask data and a live scanning-electron microscope (SEM) or scanning-ion microscope (SIM) image of the chip, along with analog and/or digital waveforms. The SEM (or SIM), layout and schematic displays in the prior-art Schlumberger systems are linked together to facilitate navigation around the IC chip. For example, when the user pans (moves laterally) or zooms (changes magnification) one of the linked displays, the others pan or zoom accordingly. When the user places a probe icon at a point on one of the linked displays, expected waveforms and actual measured waveforms at that point may be displayed for comparison.
The SEM (or SIM) image is related to the layout image much as an aerial view is related to a topographic or relief map of the same terrain. That is, the SEM (or SIM) image is the "aerial view" of the chip, and the layout image is the "topographic map." A qualitative difference is the causality; a topographical map is likely made from the aerial view, whereas the IC chip was manufactured according to the layout masks. The layout display is also linked to the schematic display in the aforementioned Schlumberger systems.
FIG. 3 illustrates an example of linked schematic, layout, and SEM images produced with an IDS 5000 system with the magnification set to produce a relatively wide field of view. The conventional Schlumberger systems display such images in multiple colors to provide the user with additional information such as the layer or net to which a particular displayed feature belongs. Schematic image 310 represents a portion of a circuit embodied in a device. Layout image 320 represents approximately the same portion of the circuit as is displayed in schematic image 310. SEM image 330 represents approximately the same portion of the circuit as is displayed in layout image 320. Examination of layout image 320 and SEM image 330 indicates a close correlation between the displayed circuit features. Superposed on layout image 320 and SEM image 330, respectively, are boxes representing a layout window 340 and a SEM window 350 which delimit the field of view of the probe for a given stage position at an increased level of magnification. That is, as the field of view is zoomed in and out in response to commands from the user, the displayed images zoom in and out correspondingly. Layout window 340 and SEM window 350 match each other closely once the images have been linked; that is, they represent approximately the same field of view of the circuit.
The charged-particle beam of the system can be directed at any location on the device lying within the field of view. In a typical operation using the prior-art systems, the operator positions an icon representing the beam at a location on a schematic or layout image to indicate a location on the device at which the beam is to be directed. FIG. 4A shows a synthetic ("layout") image 400 of a portion of an integrated circuit, generated from computer-aided design data describing the integrated circuit. FIG. 4B shows a SEM image 405 of a portion of an integrated circuit. The field of view of FIG. 4A corresponds to the field of view of FIG. 4B. Shown in the synthetic image of FIG. 4A is an icon 410 representing a location of the integrated circuit at which an electron-beam is to be directed. An icon 415 marks the corresponding location in the SEM image of FIG. 4B. Referring to FIGS. 1 and 2, data processing system 116 uses the relationship between the linked schematic/layout image information to control x-y stages 226 and/or 240 and beam deflection coils 241 to direct the beam at the selected location.
Directing a focused beam at an individual device feature which may have a dimension of 1 .mu.m or less has led to the use of high-precision x-y stages and even laser interferometers for beam positioning. Even with such equipment, accurate positioning of the beam relative to a selected device feature can be difficult and time-consuming. As geometries of circuits become smaller, keeping the CAD layout information aligned with the SEM (or SIM) image becomes more difficult. This is primarily due to errors in the stage movement and to translation errors resulting from field effects. Field effects may be global and/or local. Global field effect results in deflection of the charged-particle beam due to changing electric fields over a large area of the surface of the device being imaged, such as over a large lead frame or a large ground plane. Local field effect results in deflection of the charged-particle beam due to changing electric fields at a localized area of the device being imaged, such as when the area has latched data or is transitioning quickly between voltage levels. Such errors may demand that the system operator provide additional inputs to the system to effect fine adjustment of the beam position relative to a selected device feature after automatic positioning is completed. This need for operator intervention limits the ability to automate repetitive operations.
Methods and apparatus for registration of images are also known in the art. For example, a binocular-stereo-matching technique has been proposed for registration of a SEM image of an integrated circuit with a synthetic image generated from a database describing physical connections of the integrated circuit. The technique is influenced by Marr and Poggio's zero crossing theory, but uses the Laplacian of the Gaussian convolution sign representation with the autocorrelation function to determine disparity between two stereo images. The following steps are proposed:
Convolve grey-level images with a digital approximation of the Laplacian operator, followed by convolution with a Gaussian smoothing operator; PA1 Binarize on the convolution of the sign; PA1 Correlate regions of the binarized images using a pixel-wise exclusive-OR (EXOR) function over a range of possible displacement values in x and y, and report the displacement values at which the highest area correlation was measured.
This approach is described in U.S. Pat. No. 5,109,430, issued Apr. 28, 1992 to H. K. Nishihara et al. and U.S. patent application Ser. No. 07/731,378 filed Jul. 16, 1991 of H. K. Nishihara et al., and in H. NISHIHARA, Practical real-time imaging stereo matcher, OPTICAL ENGINEERING 23(5), September/October 1984, pp. 536-545, the contents of all of which are incorporated herein by this reference. The Nishihara et al. disclosures contemplate specialized image-processing hardware for implementing the technique, due to the undesirably long computation times required to accomplish image registration using general-purpose digital processors.